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etrontech em636165 etron technology, inc. no. 6, technology road v, science-based industrial park, hsinchu, taiwan 30077, r.o.c. tel: (886)-3-5782345 fax: (886)-3-5778671 etron technology, inc., reserves the right to make changes to its products and specifications without notice. 1mega x 16 synchronous dram (sdram) preliminary (rev. 1.8, 11/2001) features ? fast access time: 4.5/5/5/5.5/6.5/7.5 ns ? fast clock rate: 200/183/166/143/125/100 mhz ? self refresh mode: standard and low power ? fully synchronous operation ? internal pipelined architecture ? 512k x 16 bit x 2-bank ? programmable mode registers - cas# latency: 1, 2, or 3 - burst length: 1, 2, 4, 8, or full page - burst type: interleaved or linear burst - burst stop function ? individual byte controlled by ldqm and udqm ? auto refresh and self refresh ? 4096 refresh cycles/64ms ? cke power down mode ? single +3.3v 0.3v power supply ? interface: lvttl ? 50-pin 400 mil plastic tsop ii package ? 60-ball, 6.4 mm x 10.1 mm vfbga package (max total package height=1.0 mm) pin assignment (top view) key specifications em636165 -5/55/6/7/7l/8/10 t ck3 clock cycle time(min.) 5/5.5/6/7/7/8/10 ns t ras row active time(max.) 30/32/36/42/42/48/60 ns t ac3 access time from clk (max.) 4.5/5/5/5.5/5.5/6.5/7.5 ns t rc row cycle time(min.) 48/48/54/63/63/72/90 ns ordering information 1. operating temperature : 0~70 c part number frequency package EM636165TS/ve-5 200mhz tsop ii ,vfbga EM636165TS/ve-55 183mhz tsop ii ,vfbga EM636165TS/ve -6 166mhz tsop ii ,vfbga EM636165TS/ve -7 143mhz tsop ii ,vfbga EM636165TS/ve-7l 143mhz tsop ii,vfbga EM636165TS/ve -8 125mhz tsop ii,vfbga EM636165TS/ve -10 100mhz tsop ii,vfbga 2. industrial operating temperature : -40~85 c part number frequency package EM636165TS/ve -10 i 100mhz tsop ii,vfbga v dd dq 0 dq 1 v ssq dq 2 dq 3 v ddq dq 4 dq 5 v ssq dq 6 dq 7 v ddq ldqm we# ca s# ra s# cs # a11 a10 a0 a1 a2 a3 v dd vss dq15 dq14 v ssq dq13 dq12 v ddq dq11 dq10 v ssq dq 9 dq 8 v ddq nc ud qm cl k cke nc a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 a b c d e f g h vdd nc a5 a7 vss a8 dq6 dq7 clk dq8 dq9 dq3 dq1 nc dq15 dq14 dq12 vddq dq4 vddq dq11 vddq dq5 vssq udqm vssq dq10 vssq a6 vdd cke a9 a0 a10 nc nc vssq dq13 nc nc nc a11 vss a4 nc nc vddq dq2 nc nc nc ldqm we# cas# ras# cs# a3 a2 a1 j k l m n p r 123 456 7 dq0
etrontech 1m x 16 sdram em636165 preliminary 2 rev. 1.8 nov 2001 overview the em636165 sdram is a high-speed cmos synchronous dram containing 16 mbits. it is internally configured as a dual 512k x 16 bit dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 512k x 16 bit bank is organized as 2048 rows by 256 columns by 16 bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. the em636165 provides for programmable read or write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the refresh functions, either auto or self refresh are easy to use. by having a programmable mode register, the system can choose the most suitable modes to maximize its performance. these devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance pc applications. block diagram refresh counter column counter address buffer a0 a11 control signal generator ldqm udqm clock buffer command decoder column decoder sense amplifier row decoder 2048 x 256 x 16 cell array (bank #0) sense amplifier column decoder row decoder 2048 x 256 x 16 cell array (bank #1) clk cke cs# ras# cas# we# dq0 h dq15 dqs buffer mode register
etrontech 1m x 16 sdram em636165 preliminary 3 rev. 1.8 nov 2001 pin descriptions table 1. pin details of em636165 symbol type description clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. cke input clock enable: cke activates(high) and deactivates(low) the clk signal. if cke goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when both banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. cke is synchronous except after the device enters power down and self refresh modes, where cke becomes asynchronous until exiting the same mode. the input buffers, including clk, are disabled during power down and self refresh modes, providing low standby power. a11 input bank select: a11(bs) defines to which bank the bankactivate, read, write, or bankprecharge command is being applied. a0-a10 input address inputs: a0-a10 are sampled during the bankactivate command (row address a0-a10) and read/write command (column address a0-a7 with a10 defining auto precharge) to select one location out of the 256k available in the respective bank. during a precharge command, a10 is sampled to determine if both banks are to be precharged (a10 = high). the address inputs also provide the op-code during a mode register set command. cs# input chip select: cs# enables (sampled low) and disables (sampled high) the command decoder. all commands are masked when cs# is sampled high. cs# provides for external bank selection on systems with multiple banks. it is considered part of the command code. ras# input row address strobe: the ras# signal defines the operation commands in conjunction with the cas# and we# signals and is latched at the positive edges of clk. when ras# and cs# are asserted "low" and cas# is asserted "high," either the bankactivate command or the precharge command is selected by the we# signal. when the we# is asserted "high," the bankactivate command is selected and the bank designated by bs is turned on to the active state. when the we# is asserted "low," the precharge command is selected and the bank designated by bs is switched to the idle state after the precharge operation. cas# input column address strobe: the cas# signal defines the operation commands in conjunction with the ras# and we# signals and is latched at the positive edges of clk. when ras# is held "high" and cs# is asserted "low," the column access is started by asserting cas# "low." then, the read or write command is selected by asserting we# "low" or "high." we# input write enable: the we# signal defines the operation commands in conjunction with the ras# and cas# signals and is latched at the positive edges of clk. the we# input is used to select the bankactivate or precharge command and read or write command. ldqm, udqm input data input/output mask: ldqm and udqm are byte specific, nonpersistent i/o buffer controls. the i/o buffers are placed in a high-z state when ldqm/udqm is sampled high. input data is masked when ldqm/udqm is sampled high during a write cycle. output data is masked (two-clock latency) when ldqm/udqm is sampled high during a read cycle. udqm masks dq15- dq8, and ldqm masks dq7-dq0.
etrontech 1m x 16 sdram em636165 preliminary 4 rev. 1.8 nov 2001 dq0-dq15 input/output data i/o: the dq0-15 input and output data are synchronized with the positive edges of clk. the i/os are byte-maskable during reads and writes. nc - no connect: these pins should be left unconnected. v ddq supply dq power: provide isolated power to dqs for improved noise immunity. ( 3.3v 0.3v ) v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. ( 0 v ) v dd supply power supply: +3.3v 0.3v v ss supply ground
etrontech 1m x 16 sdram em636165 preliminary 5 rev. 1.8 nov 2001 operation mode fully synchronous operations are performed to latch the commands at the positive edges of clk. table 2 shows the truth table for the operation commands. table 2. truth table (note (1), (2) ) command state cke n-1 cke n dqm (6) a11 a 10 a 0-9 cs# ras# cas# we# bankactivate idle (3) h x x v v v l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) h x x v l v l h l l write and autoprecharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read and autoprecharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no-operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h clock suspend mode entry active h l x x x x x x x x power down mode entry any (5) h l x x x x h x x x l h h h clock suspend mode exit active l h x x x x x x x x power down mode exit any l h x x x x h x x x (powerdown) l h h h data write/output enable active h x l x x x x x x x data mask/output disable active h x h x x x x x x x note: 1. v=valid x=don't care l=low level h=high level 2. cke n signal is input level when commands are provided. cke n-1 signal is input level one clock cycle before the commands are provided. 3. these are states of bank designated by bs signal. 4. device state is 1, 2, 4, 8, and full page burst operation. 5. power down mode can not enter in the burst operation. when this command is asserted in the burst cycle, device state is clock suspend mode. 6. ldqm and udqm
etrontech 1m x 16 sdram em636165 preliminary 6 rev. 1.8 nov 2001 commands 1 bankprecharge command (ras# = "l", cas# = "h", we# = "l", a11 = ?v?, a10 = "l", a0-a9 = don't care) the bankprecharge command precharges the bank disignated by a11 signal. the precharged bank is switched from the active state to the idle state. this command can be asserted anytime after t ras (min.) is satisfied from the bankactivate command in the desired bank. the maximum time any bank can be active is specified by t ras (max.). therefore, the precharge function must be performed in any active bank within t ras (max.). at the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. 2 prechargeall command (ras# = "l", cas# = "h", we# = "l", a11 = don't care, a10 = "h", a0-a9 = don't care) the prechargeall command precharges both banks simultaneously and can be issued even if both banks are not in the active state. both banks are then switched to the idle state. 3 read command (ras# = "h", cas# = "l", we# = "h", a11= ?v?, a9 = "l", a0-a7 = column address) the read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the read command is issued. during read bursts, the valid data-out element from the starting column address will be available following the cas# latency after the issue of the read command. each subsequent data- out element will be valid by the next positive clock edge (refer to the following figure). the dqs go into high-impedance at the end of the burst unless other command is initiated. the burst length, burst sequence, and cas# latency are determined by the mode register, which is already programmed. a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). clk command cas# latency=1 t ck1 , dq's cas# latency=2 t ck2 , dq's cas# latency=3 t ck3 , dq's t0t 1t2t3t4t5t6t7t8 read a nop nop nop nop nop nop nop nop dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 burst read operation (burst length = 4, cas# latency = 1, 2, 3)
etrontech 1m x 16 sdram em636165 preliminary 7 rev. 1.8 nov 2001 the read data appears on the dqs subject to the values on the ldqm/udqm inputs two clocks earlier (i.e. ldqm/udqm latency is two clocks for output buffers). a read burst without the auto precharge function may be interrupted by a subsequent read or write command to the same bank or the other active bank before the end of the burst length. it may be interrupted by a bankprecharge/ prechargeall command to the same bank too. the interrupt coming from the read command can occur on any clock cycle following a previous read command (refer to the following figure). clk command cas# latency=1 t ck1 , dq's cas# latency=2 t ck2 , dq's cas# latency=3 t ck3 , dq's t0t 1t2t3t4t5t6t7t8 read a read b nop nop nop nop nop nop nop dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 read interrupted by a read (burst length = 4, cas# latency = 1, 2, 3) the ldqm/udqm inputs are used to avoid i/o contention on the dq pins when the interrupt comes from a write command. the ldqm/udqm must be asserted (high) at least two clocks prior to the write command to suppress data-out on the dq pins. to guarantee the dq pins against i/o contention, a single cycle with high-impedance on the dq pins must occur between the last read data and the write command (refer to the following three figures). if the data output of the burst read occurs at the second clock of the burst write, the ldqm/udqm must be asserted (high) at least one clock prior to the write command to avoid internal bus contention. read a nop nop nop nop write b nop nop clk dqm command dq's t0t 1 t2t3 t4t5 t6t7 t8 nop dout a 0 dinb 0 dinb 1 dinb 2 must be hi-z before the write command : "h" or "l" read to write interval (burst length 4, cas# latency = 3)
etrontech 1m x 16 sdram em636165 preliminary 8 rev. 1.8 nov 2001 clk dqm command cas# latency=1 t ck1 , dq's t0t 1 t2t3 t4t5 t6t7 t8 nop nop nop read a write a nop nop nop banka activate din a 0 din a 1 din a 2 din a 3 din a 0 din a 1 din a 2 din a 3 must be hi-z before the write command 1 clk interval cas# latency=2 t ck2 , dq's : "h" or "l" read to write interval (burst length 4, cas# latency = 1, 2) clk dqm command cas# latency=1 t ck1 , dq's t0t 1 t2t3 t4t5 t6t7 t8 nop read a nop w rite b nop nop nop din b 0 din b 1 din b 2 din b 3 din b 0 din b 1 din b 2 din b 3 must be hi-z before the write command cas# latency=2 t ck2 , dq's nop nop dout a 0 : "h" or "l" read to write interval (burst length 4, cas# latency = 1, 2) a read burst without the auto precharge function may be interrupted by a bankprecharge/ prechargeall command to the same bank. the following figure shows the optimum time that bankprecharge/ prechargeall command is issued in different cas# latency. clk command cas# latency=2 t ck2 , dq's t0t 1 t2t3 t4t5 t6t7 t8 read a nop nop nop nop activate nop nop precharge cas# latency=3 t ck3 , dq's dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 address cas# latency=1 t ck1 , dq's t rp bank, col a bank(s) bank, row read to precharge (cas# latency = 1, 2, 3)
etrontech 1m x 16 sdram em636165 preliminary 9 rev. 1.8 nov 2001 4 read and autoprecharge command (ras# = "h", cas# = "l", we# = "h", a11 = ? v ? , a10 = "h", a0-a7 = column address) the read and autoprecharge command automatically performs the precharge operation after the read operation. once this command is given, any subsequent command cannot occur within a time delay of { t rp (min.) + burst length } . at full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. 5 write command (ras# = "h", cas# = "l", we# = "l", a11 = ? v ? , a10 = "l", a0-a7 = column address) the write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the write command is issued. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). the dqs remain with high-impedance at the end of the burst unless another command is initiated. the burst length and burst sequence are determined by the mode register, which is already programmed. a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). clk command t0t 1t2t3t4t5 t6t7 t8 din a 3 nop write a nop nop nop nop nop nop nop din a 0 din a 1 din a 2 dq0 - dq3 the first data element and the write are registered on the same clock edge. extra data is masked. don't care burst write operation (burst length = 4, cas# latency = 1, 2, 3) a write burst without the auto precharge function may be interrupted by a subsequent write, bankprecharge/prechargeall, or read command before the end of the burst length. an interrupt coming from write command can occur on any clock cycle following the previous write command (refer to the following figure). clk command t0t 1t2t3t4t5t6t7t8 din b 2 nop write a nop nop nop nop nop write b nop din a 0 din b 0 din b 1 dq's din b 3 1 clk interval write interrupted by a write (burst length = 4, cas# latency = 1, 2, 3)
etrontech 1m x 16 sdram em636165 preliminary 10 rev. 1.8 nov 2001 the read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. in order to avoid data contention, input data must be removed from the dqs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). once the read command is registered, the data inputs will be ignored and writes will not be executed. clk command t0t 1 t2t3 t4t5 t6t7 t8 dout b 2 nop write a nop nop nop nop nop read b nop din a 0 dout b 0 dout b 1 cas# latency=1 t ck1 , dq's dout b 3 don't care din a 0 dout b 2 dout b 0 dout b 1 dout b 3 din a 0 don't care don't care dout b 2 dout b 0 dout b 1 dout b 3 input data for the write is masked. input data must be removed from the dq's at least one clock cycle before the read data appears on the outputs to avoid data contention. cas# latency=2 t ck2 , dq's cas# latency=3 t ck3 , dq's write interrupted by a read (burst length = 4, cas# latency = 1, 2, 3) the bankprecharge/prechargeall command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals t wr /t ck rounded up to the next whole number. in addition, the ldqm/udqm signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the bankprecharge/prechargeall command is entered (refer to the following figure). clk t0t 1t2t3t4t5 t6 write command bank (s) row nop nop precharge nop nop activate bank col n din n din n + 1 dqm address dq t wr t rp : don't care note: the ldqm/udqm can remain low in this example if the length of the write burst is 1 or 2. write to precharge
etrontech 1m x 16 sdram em636165 preliminary 11 rev. 1.8 nov 2001 6 write and autoprecharge command (refer to the following figure) (ras# = "h", cas# = "l", we# = "l", a11 = ? v ? , a10 = "h", a0-a7 = column address) the write and autoprecharge command performs the precharge operation automatically after the write operation. once this command is given, any subsequent command can not occur within a time delay of { (burst length -1) + t wr + t rp (min.) } . at full-page burst, only the write operation is performed in this command and the auto precharge function is ignored. clk command t0t 1 t2t3 t4t5 t6t7 t8 nop nop nop nop nop nop nop din a 0 din a 1 cas# latency=1 t ck1 , dq's cas# latency=2 t ck2 , dq's cas# latency=3 t ck3 , dq's din a 0 din a 1 din a 0 din a 1 t dal * * * t dal = t wr + t rp * begin autoprecharge bank can be reactivated at completion of t dal bank a activate write a autoprecharge t dal t dal burst write with auto-precharge (burst length = 2, cas# latency = 1, 2, 3) 7 mode register set command (ras# = "l", cas# = "l", we# = "l", a11 = ? v ? , a10 = ? v ? , a0-a9 = register data) the mode register stores the data for controlling the various operating modes of sdram. the mode register set command programs the values of cas# latency, addressing mode and burst length in the mode register to make sdram useful for a variety of different applications. the default values of the mode register after power-up are undefined; therefore this command must be issued at the power-up sequence. the state of pins a0~a9 and a11 in the same cycle is the data written to the mode register. one clock cycle is required to complete the write in the mode register (refer to the following figure). the contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as both banks are in the idle state.
etrontech 1m x 16 sdram em636165 preliminary 12 rev. 1.8 nov 2001 ras# t0 t 1 t2 t3 t4t5 t6t7 t8t9 t10 clk cke cs# cas# we# a11 a10 a0-a9 dqm dq t ck2 clock min. address key t rp hi-z prechargeall mode register set command any command mode register set cycle (cas# latency = 1, 2, 3) the mode register is divided into various fields depending on functionality. ? burst length field (a2~a0) this field specifies the data length of column access using the a2~a0 pins and selects the burst length to be 1, 2, 4, 8, or full page. a2 a1 a0 burst length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 full page
etrontech 1m x 16 sdram em636165 preliminary 13 rev. 1.8 nov 2001 ? addressing mode select field (a3) the addressing mode can be one of two modes, interleave mode or sequential mode. sequential mode supports burst length of 1, 2, 4, 8, or full page, but interleave mode only supports burst length of 4 and 8. a3 addressing mode 0 sequential 1 interleave --- addressing sequence of sequential mode an internal column address is performed by increasing the address from the column address which is input to the device. the internal column address is varied by the burst length as shown in the following table. when the value of column address, (n + m), in the table is larger than 255, only the least significant 8 bits are effective. data n 0 1 2 3 4 5 6 7 - 255 256 257 - column address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 - 2 words: burst length 4 words: 8 words: full page: column address is repeated until terminated. --- addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. data n column address burst length data 0 a7 a6 a5 a4 a3 a2 a1 a0 data 1 a7 a6 a5 a4 a3 a2 a1 a0# 4 words data 2 a7 a6 a5 a4 a3 a2 a1# a0 data 3 a7 a6 a5 a4 a3 a2 a1# a0# 8 words data 4 a7 a6 a5 a4 a3 a2# a1 a0 data 5 a7 a6 a5 a4 a3 a2# a1 a0# data 6 a7 a6 a5 a4 a3 a2# a1# a0 data 7 a7 a6 a5 a4 a3 a2# a1# a0# ? cas# latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the first read data. the minimum whole value of cas# latency depends on the frequency of clk. the minimum whole value satisfying the following formula must be programmed into this field. t cac (min) cas# latency x t ck a6 a5 a4 cas# latency 0 0 0 reserved 0 0 1 1 clock 0 1 0 2 clocks 0 1 1 3 clocks 1 x x reserved
etrontech 1m x 16 sdram em636165 preliminary 14 rev. 1.8 nov 2001 ? test mode field (a8~a7) these two bits are used to enter the test mode and must be programmed to "00" in normal operation. a8 a7 test mode 0 0 normal mode 0 1 vendor use only 1 x vendor use only ? single write mode (a9) this bit is used to select the write mode. when the bs bit is "0", the burst-read-burst- write mode is selected. when the bs bit is "1", the burst-read-single-write mode is selected. a9 single write mode 0 burst-read-burst-write 1 burst-read-single-write note: a10 and a11 should stay ? l ? during mode set cycle. 8 no-operation command (ras# = "h", cas# = "h", we# = "h") the no-operation command is used to perform a nop to the sdram which is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. 9 burst stop command (ras# = "h", cas# = "h", we# = "l") the burst stop command is used to terminate either fixed-length or full-page bursts. this command is only effective in a read/write burst without the auto precharge function. the terminated read burst ends after a delay equal to the cas# latency (refer to the following figure). the termination of a write burst is shown in the following figure. clk command t0t 1t2t3t4t5 t6t7 t8 read a nop nop nop nop nop nop nop burst stop dout a 0 dout a 1 dout a 2 dout a 3 cas# latency=1 t ck1 , dq's cas# latency=2 t ck2 , dq's cas# latency=3 t ck3 , dq's dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 the burst ends after a delay equal to the cas# latency. termination of a burst read operation (burst length 4, cas# latency = 1, 2, 3)
etrontech 1m x 16 sdram em636165 preliminary 15 rev. 1.8 nov 2001 clk command t0t 1t2t3t4t5 t6t7 t8 nop write a nop nop nop nop nop nop burst stop cas# latency=1, 2, 3 dq's din a 0 din a 1 din a 2 don't care input data for the write is masked. termination of a burst write operation (burst length = x, cas# latency = 1, 2, 3) 10 device deselect command (cs# = "h") the device deselect command disables the command decoder so that the ras#, cas#, we# and address inputs are ignored, regardless of whether the clk is enabled. this command is similar to the no operation command. 11 autorefresh command (refer to figures 3 & 4 in timing waveforms) (ras# = "l", cas# = "l", we# = "h",cke = "h", a11 = ? don ? t care, a0-a9 = don't care) the autorefresh command is used during normal operation of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conventional drams. this command is non-persistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a "don't care" during an autorefresh command. the internal refresh counter increments automatically on every auto refresh cycle to all of the rows. the refresh operation must be performed 2048 times within 32ms. the time required to complete the auto refresh operation is specified by t rc (min.). to provide the autorefresh command, both banks need to be in the idle state and the device must not be in power down mode (cke is high in the previous cycle). this command must be followed by nops until the auto refresh operation is completed. the precharge time requirement, t rp (min), must be met before successive auto refresh operations are performed. 12 selfrefresh entry command (refer to figure 5 in timing waveforms) (ras# = "l", cas# = "l", we# = "h", cke = "l", a0-a9 = don't care) the selfrefresh is another refresh mode available in the sdram. it is the preferred refresh mode for data retention and low power operation. once the selfrefresh command is registered, all the inputs to the sdram become "don't care" with the exception of cke, which must remain low. the refresh addressing and timing is internally generated to reduce power consumption. the sdram may remain in selfrefresh mode for an indefinite period. the selfrefresh mode is exited by restarting the external clock and then asserting high on cke (selfrefresh exit command). 13 selfrefresh exit command (refer to figure 5 in timing waveforms) (cke = "h", cs# = "h" or cke = "h", ras# = "h", cas# = "h", we# = "h") this command is used to exit from the selfrefresh mode. once this command is registered, nop or device deselect commands must be issued for t rc (min.) because time is required for the completion of any bank currently being internally refreshed. if auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the selfrefresh mode.
etrontech 1m x 16 sdram em636165 preliminary 16 rev. 1.8 nov 2001 14 clock suspend mode entry / powerdown mode entry command (refer to figures 6, 7, and 8 in timing waveforms) (cke = "l") when the sdram is operating the burst cycle, the internal clk is suspended(masked) from the subsequent cycle by issuing this command (asserting cke "low"). the device operation is held intact while clk is suspended. on the other hand, when both banks are in the idle state, this command performs entry into the powerdown mode. all input and output buffers (except the cke buffer) are turned off in the powerdown mode. the device may not remain in the clock suspend or powerdown state longer than the refresh period (64ms) since the command does not perform any refresh operations. 15 clock suspend mode exit / powerdown mode exit command (refer to figures 6, 7, and 8 in timing waveforms, cke= "h") when the internal clk has been suspended, the operation of the internal clk is reinitiated from the subsequent cycle by providing this command (asserting cke "high"). when the device is in the powerdown mode, the device exits this mode and all disabled buffers are turned on to the active state. t pde (min.) is required when the device exits from the powerdown mode. any subsequent commands can be issued after one clock cycle from the end of this command. 16 data write / output enable, data mask / output disable command (ldqm/udqm = "l", "h") during a write cycle, the ldqm/udqm signal functions as a data mask and can control every word of the input data. during a read cycle, the ldqm/udqm functions as the controller of output buffers. ldqm/udqm is also used for device selection, byte selection and bus control in a memory system. ldqm controls dq0 to dq7, udqm controls dq8 to dq15.
etrontech 1m x 16 sdram em636165 preliminary 17 rev. 1.8 nov 2001 absolute maximum rating symbol item rating unit note -5/55/6/7/7l/8/10 -10 i v in , v out input, output voltage - 1.0 ~ 4.6 v 1 v dd , v ddq power supply voltage -1.0 ~ 4.6 v 1 t opr operating temperature 0 ~ 70 -40 ~ 85 c 1 t stg storage temperature - 55 ~ 125 c 1 p d power dissipation 1 0.6 w 1 i out short circuit output current 50 ma 1 recommended d.c. operating conditions (ta = -40~85 c) symbol parameter min. typ. max. unit note v dd power supply voltage 3.0 3.3 3.6 v 2 v ddq power supply voltage(for i/o buffer) 3.0 3.3 3.6 v 2 v ih lvttl input high voltage 2.0 v ddq +0.3 v 2 v il lvttl input low voltage - 0.3 0.8 v 2 capacitance (v dd = 3.3v, f = 1mhz, ta = 25 c) symbol parameter min. max. unit c i input capacitance 2 5 pf c i/o input/output capacitance 4 7 pf note: these parameters are periodically sampled and are not 100% tested. recommended d.c. operating conditions (v dd = 3.3v 0.3v) 1. ta = 0~70 c - 5/55/6/7/8/10 - 7l description/test condition symbol max. unit note operating current t rc t rc (min), outputs open, input signal one transition per one cycle 1 bank operation i dd1 130/125/115/100/95 /85 40 3 precharge standby current in non-power down mode t ck = t ck (min), cs# v ih , cke = v ih input signals are changed once during 30ns. i dd2n 115/110/90/85/75/60 15 3 precharge standby current in power down mode t ck = t ck (min), cke v il (max) i dd2p 2 0.8 3 precharge standby current in power down mode t ck = - cke v il (max) i dd2ps 2 0.8 active standby current in power down mode cke v il (max), t ck = t ck (min) i dd3p 2 1.5 ma 3 active standby current in non-power down mode cke v ih (min), t ck = t ck (min) i dd3n 105/100/90/80/70/55 20 operating current (burst mode) t ck =t ck (min), outputs open, multi-bank interleave,gapless data i dd4 165/160/150/140/130/115 40 3, 4 refresh current t rc t rc (min) i dd5 115/110/100/90/90 /80 40 3 self refresh current v ih v dd - 0.2, 0v v il 0.2v i dd6 2 0.5
etrontech 1m x 16 sdram em636165 preliminary 18 rev. 1.8 nov 2001 2. industrial operating temperature : ta = -40~85 c em636165-10 i description/test condition symbol max. unit note operating current t rc t rc (min), outputs open, input signal one transition per one cycle 1 bank operation i dd1 80 3 precharge standby current in non-power down mode t ck = t ck (min), cs# v ih , cke = v ih input signals are changed once during 30ns. i dd2n 35 3 precharge standby current in power down mode t ck = t ck (min), cke v il (max) i dd2p 3 3 precharge standby current in power down mode t ck = - cke v il (max) i dd2ps 2 ma active standby current in power down mode cke v il (max), t ck = t ck (min) i dd3p 7 3 active standby current in non-power down mode cke v ih (min), t ck = t ck (min) i dd3n 51 operating current (burst mode) t ck =t ck (min), outputs open, multi-bank interleave,gapless data i dd4 100 3, 4 refresh current t rc t rc (min) i dd5 80 3 self refresh current v ih v dd - 0.2, 0v v il 0.2v i dd6 2 parameter description min. max. unit note i il input leakage current ( 0v v in v dd , all other pins not under test = 0v ) - 10 10 a i ol output leakage current output disable, 0v v out v ddq ) - 10 10 a v oh lvttl output "h" level voltage ( i out = -2ma ) 2.4 v v ol lvttl output "l" level voltage ( i out = 2ma ) 0.4 v
etrontech 1m x 16 sdram em636165 preliminary 19 rev. 1.8 nov 2001 electrical characteristics and recommended a.c. operating conditions (v dd = 3.3v 2 0.3v, ta = -40~85 c) (note: 5, 6, 7, 8) - 5/55/6/7/7l/8/10 symbol a.c. parameter min. max. unit note t rc row cycle time (same bank) 48/48/54/63/63/72/90 9 t rcd ras# to cas# delay (same bank) 15/16/16/16/16/16/30 9 t rp precharge to refresh/row activate command (same bank) 15/16/16/16/16/16/30 ns 9 t rrd row activate to row activate delay (different banks) 10/11/12/14/14/16/20 9 t ras row activate to precharge time (same bank) 30/32/36/42/42/48/60 100,000 t wr write recovery time 1 cycle t ck1 cl* = 1 -/19/20/20/20/20/30 t ck2 clock cycle time cl* = 2 -/7/7.5/8/8/8/15 10 t ck3 cl* = 3 5/5.5/6/7/7/8/10 t ch clock high time 2/2/2/2.5/2.5/3/3.5 ns 11 t cl clock low time 2/2/2/2.5/2.5/3/3.5 11 t ac1 access time from clk cl* = 1 -/7/8/13/13/18/27 t ac2 (positive edge) cl* = 2 -/5.5/6/6.5/6.5/7/12 11 t ac3 cl* = 3 4.5/5/5/5.5/5.5/6.5/7.5 t ccd cas# to cas# delay time 1 cycle t oh data output hold time 1.8/2/2/2/2/2/3 10 t lz data output low impedance 1/1/1/1/1/2/2 t hz data output high impedance 3/3.5/4/5/5/6/8 8 t is data/address/control input set-up time 2/2/2/2/2/2.5/3 ns 11 t ih data/address/control input hold time 1 11 t pde powerdown exit set-up time 5/5.5/6/7/7/8/10 t ref refresh time 64 ms + cl is cas# latency. note: 1. stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. 2. all voltages are referenced to v ss .v ih (max)=4.6 for pulse width 5ns.v il (min)=-1.5vfor pulse width 5ns. 3. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . 4. these parameters depend on the output loading. specified values are obtained with the output open. 5. power-up sequence is described in note 10.
etrontech 1m x 16 sdram em636165 preliminary 20 rev. 1.8 nov 2001 6. a.c. test conditions lvttl interface reference level of output signals 1.4v / 1.4v output load reference to the under output load (b) input signal levels 2.4v / 0.4v transition time (rise and fall) of input signals 1ns reference level of input signals 1.4v 3.3v 1.2k ? 870 ? 30pf output 1.4v 50 ? output 30pf 50 ? z0= lvttl d.c. test load (a) lvttl a.c. test load (b) 7. transition times are measured between v ih and v il . transition(rise and fall) of input signals are in a fixed slope (1 ns). 8. t hz defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. these parameters account for the number of clock cycle and depend on the operating frequency of the clock as follows: the number of clock cycles = specified value of timing/clock cycle time (count fractions as a whole number) 10.if clock rising time is longer than 1 ns, ( t r / 2 -0.5) ns should be added to the parameter. 11.assumed input rise and fall time t t ( t r & t f ) = 1 ns if t r or t f is longer than 1 ns, transient time compensation should be considered, i.e., 12. power up sequence power up must be performed in the following sequence. 1) power must be applied to v dd and v ddq (simultaneously) when all input signals are held "nop" state and both cke = "h" and ldqm/udqm = "h." the clk signals must be started at the same time. 2) after power-up, a pause of 200 seconds minimum is required. then, it is recommended that ldqm/udqm is held "high" (v dd levels) to ensure dq output is in high impedance. 3) both banks must be precharged. 4) mode register set command must be asserted to initialize the mode register. 5) a minimum of 2 auto-refresh dummy cycles must be required to stabilize the internal circuitry of the device.
etrontech 1m x 16 sdram em636165 preliminary 21 rev. 1.8 nov 2001 timing waveforms figure 1. ac parameters for write timing (burst length=4, cas# latency=2) a11 t0t 1t2t3t4t5t6t7t8t9t10t11t12t13t14t15t16t17t18t19t20t21t22 t ch t cl t ck2 t is t is t ih begin autoprecharge bank a begin autoprecharge bank b t is t ih t is rax rbx rbx cax rbx cbx ray ray cay raz raz rby rby t rcd t dal t rc t is t ih t wr t rp t rrd ax0 ax1 ax2 ax3 bx0 bx1 bx2 bx3 ay0 ay1 ay2 ay3 activate co mm an d bank a write with autoprecharge co mm an d bank a activate co mm an d bank b write with autoprecharge co mm and bank b activate co mm an d bank a write co mm an d bank a precharge co mm an d bank a activate co mm and bank a activate co mm and bank b clk cke cs# ras# cas# we# a10 a0-a9 dqm dq hi-z
etrontech 1m x 16 sdram em636165 preliminary 22 rev. 1.8 nov 2001 figure 2. ac parameters for read timing (burst length=2, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t 11 t12 t13 clk cke cs# ras# cas# we# a11 a10 a0-a9 dqm dq t ch t cl t ck2 t is t is t ih begin autoprecharge bank b t ih t ih t is rax rax cax rbx rbx cbx ray ray t rrd t ras t rc t rcd t ac2 t lz t oh t hz ax0 ax1 bx0 bx1 t rp activate co mm an d bank a rea d co mm an d bank a activate co mm an d bank b read with auto precharge co mm an d bank b precharge co mm an d bank a activate co mm an d bank a hi-z t ac2 t hz
etrontech 1m x 16 sdram em636165 preliminary 23 rev. 1.8 nov 2001 figure 3. auto refresh (cbr) (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a11 a10 a0-a9 dqm dq t ck2 rax rax t rp t rc ax0 ax1 ax2 prechargeall co mm an d autorefresh co mm an d autorefresh co mm an d activate co mm an d bank a rea d co mm an d bank a t rc ax3 cax
etrontech 1m x 16 sdram em636165 preliminary 24 rev. 1.8 nov 2001 figure 4. power on sequene and auto refresh (cbr) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# bs a10 a0-a9 dqm dq t ck2 high level is reauired minimum of 2 refresh cycles are required hi-z t rp t rc address key inputs must be stable for 200
etrontech 1m x 16 sdram em636165 preliminary 25 rev. 1.8 nov 2001 figure 5. self refresh entry & exit cycle clk cke cs# ras# cas# a11 a0-a9 we# dqm t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 dq * note 1 *note 2 t is *note 3 *note 4 t rc(min) *note 7 *note 5 *note 6 *note 8 *note 8 hi-z hi-z self refresh enter selfrefresh exit autorefresh t srx t pde note: to enter selfrefresh mode 1. cs#, ras# & cas# with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don't care except for cke. 3. the device remains in selfrefresh mode as long as cke stays "low". once the device enters selfrefresh mode, minimum t ras is required before exit from selfrefresh. to exit selfrefresh mode 1. system clock restart and be stable before returning cke high. 2. enable cke and cke should be set high for minimum time of t srx . 3. cs# starts from high. 4. minimum t rc is required after cke going high to complete selfrefresh exit. 5. 2048 cycles of burst autorefresh is required before selfrefresh entry and after selfrefresh exit if the system uses burst refresh.
etrontech 1m x 16 sdram em636165 preliminary 26 rev. 1.8 nov 2001 figure 6.1. clock suspension during burst read (using cke) (burst length=4, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t8 t9 t10 t11 t13 t14 t15 t16 t17 t19 t20 t21 t22 clk cke cs# ras# cas# we# a11 a10 a0-a9 dqm dq t ck1 rax rax cax hi-z ax0 ax1 ax2 ax3 activate co mm and bank a read co mm and bank a clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles t hz t7 t12 t18 note: cke to clk disable/enable = 1 clock
etrontech 1m x 16 sdram em636165 preliminary 27 rev. 1.8 nov 2001 figure 6.2. clock suspension during burst read (using cke) (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a11 a10 a0-a9 dqm dq t ck2 rax rax cax hi-z ax0 ax1 ax2 ax3 activate co mm and bank a read co mm and bank a clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles t hz note: cke to clk disable/enable = 1 clock
etrontech 1m x 16 sdram em636165 preliminary 28 rev. 1.8 nov 2001 figure 6.3. clock suspension during burst read (using cke) (burst length=4, cas# latency=3) t0 t 1 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a11 a10 a0-a9 dqm dq t ck3 rax rax cax hi-z ax0 ax1 ax2 ax3 activate co mm and bank a read co mm an d bank a clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles t hz t 2 note: cke to clk disable/enable = 1 clock
etrontech 1m x 16 sdram em636165 preliminary 29 rev. 1.8 nov 2001 figure 7.1. clock suspension during burst write (using cke) (burst length = 4, cas# latency = 1) t0t 1t2t3t4t5t6t7t8t9t10t11t12t13t14t15t16t17t18t19t20t21t22 clk cke cs# ras# cas# we# a11 a10 a0-a8 dqm dq t ck1 rax rax cax hi-z dax0 activate co mm an d bank a write co mm an d bank a clock suspend 2 cycles clock suspend 3 cycles dax1 dax2 dax3 clock suspend 1 cycle note: cke to clk disable/enable = 1 clock
etrontech 1m x 16 sdram em636165 preliminary 30 rev. 1.8 nov 2001 figure 7.2. clock suspension during burst write (using cke) (burst length=4, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke cs# ras# cas# we# a11 a10 a0-a9 dqm dq t ck2 rax rax cax hi-z dax0 activate co mm an d bank a write co mm and bank a clock suspend 2 cycles clock suspend 3 cycles dax1 dax2 dax3 clock suspend 1 cycle t22 note: cke to clk disable/enable = 1 clock
etrontech 1m x 16 sdram em636165 preliminary 31 rev. 1.8 nov 2001 figure 7.3. clock suspension during burst write (using cke) (burst length=4, cas# latency=3) t0t 1t2t3t4t5t6t7t8t9t10t11t12t13t14t15t16t17t18t19t20t21t22 clk cke cs# ras# cas# we# a11 a10 a0-a9 dqm dq dax1 dax2 dax3 t ck3 rax rax cax hi-z activate co mm and bank a write co mm and bank a clock suspend 2 cycles clock suspend 3 cycles clock suspend 1 cycle dax0 note: cke to clk disable/enable = 1 clock
etrontech 1m x 16 sdram em636165 preliminary 32 rev. 1.8 nov 2001 figure 8. power down mode and clock mask (burst lenght=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a11 a10 a0~a8 dqm dq t ck2 t is t pde rax rax cax t hz ax3 ax2 ax1 ax0 activate co mm and bank a power down mode entry power down mode exit read co mm an d bank a clock mask start clock mask end precharge co mm and bank a power down mode entry precharge standby any co mm an d power down mode exit hi-z valid active standby
etrontech 1m x 16 sdram em636165 preliminary 33 rev. 1.8 nov 2001 figure 9.1. random column read (page within same bank) (burst length=4, cas# latency=1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a8 dqm dq a11 t ck1 activate co mm an d bank a read co mm an d bank a rea d co mm an d bank a precharge co mm an d bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 raw raw caw cax cay rea d co mm an d bank a hi-z caz az0 az1 az2 az3 rea d co mm an d bank a activate co mm an d bank a raz raz
etrontech 1m x 16 sdram em636165 preliminary 34 rev. 1.8 nov 2001 figure 9.2. random column read (page within same bank) (burst length=4, cas# latency=2) t0t 1t2t3t4t5t6t7t8t9t10t11t12t13t14t15t16t17t18t19t20t21t22 clk cke cs# ras# cas# we# a10 a0~a8 dqm dq a11 t ck2 activate co mm an d bank a read co mm an d bank a rea d co mm an d bank a precharge co mm an d bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 raw raw caw cax cay rea d co mm an d bank a hi-z caz az0 az1 az2 az3 read co mm an d bank a activate co mm an d bank a raz raz
etrontech 1m x 16 sdram em636165 preliminary 35 rev. 1.8 nov 2001 figure 9.3. random column read (page within same bank) (burst length=4, cas# latency=3) t0t 1t2t3t4t5t6t7t8t9t10t11t12t13t14t15t16t17t18t19t20t21t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a1 1 t ck3 activate co mm an d bank a read co mm an d bank a rea d co mm an d bank a precharge co mm an d bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 raw raw caw cax cay rea d co mm an d bank a hi-z caz rea d co mm an d bank a activate co mm an d bank a raz raz az0
etrontech 1m x 16 sdram em636165 preliminary 36 rev. 1.8 nov 2001 figure 10.1. random column write (page within same bank) (burst length=4, cas# latency=1) t0t 1t2t3t4t5t6t7t8t9t10t11t12t13t14t15t16t17t18t19t20t21t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck1 activate co mm an d bank a write co mm an d bank a write co mm an d bank b precharge co mm an d bank b dbw0 dbw1 dbw2 dbw3 dbx0 dbx1 dby0 dby1 dby2 dby3 rbw rbw cbw cbx cby write co mm an d bank b hi-z cbz dbz0 dbz1 dbz2 dbz3 write co mm an d bank b activate co mm an d bank b rbz rbz
etrontech 1m x 16 sdram em636165 preliminary 37 rev. 1.8 nov 2001 figure 10.2. random column write (page within same bank) (burst length=4, cas# latency=2) t0t 1t2t3t4t5t6t7t8t9t10t11t12t13t14t15t16t17t18t19t20t21t22 clk cke cs# ras# cas# we# a10 a0~a8 dqm dq a11 t ck2 activate co mm an d bank a write co mm an d bank b write co mm an d bank b precharge co mm an d bank b dbw0 dbw1 dbw2 dbw3 dbx0 dbx1 dby0 dby1 dby2 dby3 rbw rbw cbw cbx cby write co mm an d bank b hi-z cbz dbz0 dbz1 dbz2 dbz3 write co mm an d bank b activate co mm an d bank b rbz rbz
etrontech 1m x 16 sdram em636165 preliminary 38 rev. 1.8 nov 2001 figure 10.3. random column write (page within same bank) (burst length=4, cas# latency=3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck3 activate co mm an d bank a write co mm an d bank b write co mm an d bank b precharge co mm an d bank b dbw0 dbw1 dbw2 dbw3 dbx0 dbx1 dby0 dby1 dby2 dby3 rbw rbw cbw cbx cby write co mm an d bank b hi-z cbz dbz0 dbz1 write co mm an d bank b activate co mm an d bank b rbz rbz dbz2
etrontech 1m x 16 sdram em636165 preliminary 39 rev. 1.8 nov 2001 figure 11.1. random row read (interleaving banks) (burst length=8, cas# latency=1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck1 activate co mm an d bank b activate co mm an d bank a precharge co mm an d bank b bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 rbx rbx rby rea d co mm an d bank b hi-z cby read co mm an d bank b precharge co mm an d bank a high rax read co mm an d bank a activate co mm an d bank b by0 by1 by2 ax2 ax3 ax4 ax5 ax6 ax7 cbx cax rax rby t rcd t ac1 t rp
etrontech 1m x 16 sdram em636165 preliminary 40 rev. 1.8 nov 2001 figure 11.2. random row read (interleaving banks) (burst length=8, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck2 activate co mm an d bank b activate co mm an d bank a precharge co mm an d bank b bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 rbx rbx rby rea d co mm an d bank b hi-z cby rea d co mm an d bank b high rax read co mm an d bank a activate co mm an d bank b by0 by1 ax2 ax3 ax4 ax5 ax6 ax7 cbx cax rax rby t rcd t ac2 t rp
etrontech 1m x 16 sdram em636165 preliminary 41 rev. 1.8 nov 2001 figure 11.3. random row read (interleaving banks) (burst length=8, cas# latency=3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck3 activate co mm an d bank b activate co mm an d bank a precharge co mm an d bank b bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 rbx rbx rby read co mm an d bank b hi-z cby rea d co mm an d bank b high rax rea d co mm an d bank a activate co mm an d bank b ax7 by0 ax2 ax3 ax4 ax5 ax6 cbx cax rax rby t rcd t ac3 t rp precharge co mm an d bank a
etrontech 1m x 16 sdram em636165 preliminary 42 rev. 1.8 nov 2001 figure 12.1. random row write (interleaving banks) (burst length=8, cas# latency=1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck1 activate co mm an d bank a activate co mm an d bank b precharge co mm an d bank a dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 rax rax ray write co mm an d bank a hi-z cay high rbx precharge co mm an d bank b dbx7 day3 dbx2 dbx3 dbx4 dbx5 dbx6 cax cbx rbx ray t rcd day0 day1 day2 write co mm an d bank a write co mm an d bank b activate co mm an d bank a t rp t wr
etrontech 1m x 16 sdram em636165 preliminary 43 rev. 1.8 nov 2001 figure 12.2. random row write (interleaving banks) (burst length=8, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a8 dqm dq a11 t ck2 activate co mm an d bank a activate co mm an d bank b precharge co mm an d bank a dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 rax rax ray write co mm an d bank a hi-z cay high rbx precharge co mm an d bank b dbx7 dbx2 dbx3 dbx4 dbx5 dbx6 cax cbx rbx ray t rcd write co mm an d bank a write co mm an d bank b activate co mm an d bank a day3 day0 day1 day2 day4 t wr* t rp t wr* * t wr > t wr (min.)
etrontech 1m x 16 sdram em636165 preliminary 44 rev. 1.8 nov 2001 figure 12.3. random row write (interleaving banks) (burst length=8, cas# latency=3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck3 activate co mm an d bank a activate co mm an d bank b precharge co mm an d bank a dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 rax rax ray write co mm an d bank a hi-z cay high rbx precharge co mm an d bank b dbx7 dbx2 dbx3 dbx4 dbx5 dbx6 cax cbx rbx ray t rcd write co mm an d bank a write co mm an d bank b activate co mm an d bank a day3 day0 day1 day2 t wr* t rp t wr* * t wr > t wr (min.)
etrontech 1m x 16 sdram em636165 preliminary 45 rev. 1.8 nov 2001 figure 13.1. read and write cycle (burst length=4, cas# latency=1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck1 activate co mm an d bank a the write data is masked with a zero clock latency rea d co mm an d bank a ax0 ax1 ax2 ax3 day0 day1 hi-z precharge co mm an d bank b az3 day3 az0 az1 rea d co mm an d bank a write co mm an d bank a the read data is masked with a two clock latency rax rax cax cay caz
etrontech 1m x 16 sdram em636165 preliminary 46 rev. 1.8 nov 2001 figure 13.2. read and write cycle (burst length=4, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck2 activate co mm an d bank a the write data is masked with a zero clock latency read co mm an d bank a ax0 ax1 ax2 ax3 day0 day1 hi-z az3 day3 az0 az1 read co mm an d bank a write co mm an d bank a the read data is masked with a two clock latency rax rax cax cay caz
etrontech 1m x 16 sdram em636165 preliminary 47 rev. 1.8 nov 2001 figure 13.3. read and write cycle (burst length=4, cas# latency=3) t0t 1t2t3t4t5t6t7t8t9t10t11t12t13t14t15t16t17t18t19t20t21t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck3 activate co mm an d bank a the write data is masked with a zero clock latency rea d co mm an d bank a ax0 ax1 ax2 ax3 day0 day1 hi-z az3 day3 az0 az1 rea d co mm an d bank a write co mm an d bank a the read data is masked with a two clock latency rax rax cax cay caz
etrontech 1m x 16 sdram em636165 preliminary 48 rev. 1.8 nov 2001 figure 14.1. interleaving column read cycle (burst length=4, cas# latency=1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck1 activate co mm an d bank a read co mm an d bank b precharge co mm and bank a bw0 bw1 bx0 bx1 by1 ay0 hi-z bz0 read co mm an d bank a read co mm an d bank a rax rax ax0 ax1 ax2 ax3 by0 ay1 bz1 bz2 bz3 activate co mm an d bank b read co mm an d bank b read co mm an d bank b read co mm an d bank b precharge co mm an d bank b t rcd t ac1 rax rbw rbw cbw cbx cby cay cbz
etrontech 1m x 16 sdram em636165 preliminary 49 rev. 1.8 nov 2001 figure 14.2. interleaving column read cycle (burst length=4, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck2 activate co mm an d bank a rea d co mm an d bank b precharge co mm an d bank a bw0 bw1 bx0 bx1 by1 ay0 hi-z bz0 read co mm an d bank a rea d co mm an d bank a rax rax ax0 ax1 ax2 ax3 by0 ay1 bz1 bz2 bz3 activate co mm an d bank b read co mm an d bank b rea d co mm an d bank b rea d co mm an d bank b precharge co mm an d bank b t rcd t ac2 cay rax rax cbw cbx cby cay cbz
etrontech 1m x 16 sdram em636165 preliminary 50 rev. 1.8 nov 2001 figure 14.3. interleaved column read cycle (burst length=4, cas# latency=3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck3 activate co mm an d bank a prechaerge co mm an d bank b bx0 bx1 by0 by1 bz1 ay0 hi-z ay2 read co mm an d bank a read co mm an d bank a rax rax ax0 ax1 ax2 ax3 bz0 ay1 ay3 activate co mm an d bank b read co mm an d bank b read co mm an d bank b read co mm an d bank b precharge co mm an d bank a t rcd t ac3 cax rbx rbx cbx cby cbz cay
etrontech 1m x 16 sdram em636165 preliminary 51 rev. 1.8 nov 2001 figure 15.1. interleaved column write cycle (burst length=4, cas# latency=1) t0 t1 t2 t3 t4 t5 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck1 activate co mm an d bank a write co mm an d bank b dbw0 dbw1 dbx0 dbx1 dby1 day0 hi-z write co mm an d bank a precharge co mm and bank a rax rax dax0 dax1 dax2 dax3 dby0 day1 dbz0 activate co mm an d bank b write co mm and bank b write co mm an d bank b write co mm and bank a precharge co mm an d bank b t rcd cax rbw rbw cbw cbx cby cay dbz1 dbz2 dbz3 write co mm an d bank b t rrd t rp t wr t rp cbz t6
etrontech 1m x 16 sdram em636165 preliminary 52 rev. 1.8 nov 2001 figure 15.2. interleaved column write cycle (burst length=4, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# a10 a0~a9 dqm dq a11 t ck2 activate co mm and bank a write co mm an d bank b dbw0 dbw1 dbx0 dbx1 dby1 day0 hi-z write co mm and bank a precharge co mm and bank a rax rax dax0 dax1 dax2 dax3 dby0 day1 dbz0 activate co mm an d bank b write co mm an d bank b write co mm an d bank b write co mm and bank a precharge co mm and bank b t rcd cax rbw rbw cbw cbx cby cay dbz1 dbz2 dbz3 write co mm and bank b t rrd t rp t wr t rp cbz we#
etrontech 1m x 16 sdram em636165 preliminary 53 rev. 1.8 nov 2001 figure 15.3. interleaved column write cycle (burst length=4, cas# latency=3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# a10 a0~a9 dqm dq a11 t ck3 activate co mm an d bank a write co mm an d bank b dbw0 dbw1 dbx0 dbx1 dby1 day0 hi-z write co mm an d bank a precharge co mm an d bank a rax rax dax0 dax1 dax2 dax3 dby0 day1 dbz0 activate co mm an d bank b write co mm an d bank b write co mm an d bank b write co mm an d bank a precharge co mm an d bank b t rcd cax rbw rbw cbw cbx cby cay dbz1 dbz2 dbz3 write co mm an d bank b t rrd > t rrd(min) t rp t wr t wr(min) cbz we#
etrontech 1m x 16 sdram em636165 preliminary 54 rev. 1.8 nov 2001 figure 16.1. auto precharge after read burst (burst length=4, cas# latency=1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck1 activate co mm an d bank a activate co mm an d bank b bx0 bx1 bx2 bx3 ay1 ay2 hi-z read co mm an d bank a rax rax rbx ax0 ax1 ax2 ax3 ay0 ay3 by0 activate co mm an d bank b activate co mm an d bank b rbx cbx cay rby cby by1 by2 by3 rbz high bz0 bz1 bz2 bz3 read with auto precharge co mm an d bank b read with auto precharge co mm an d bank a read with auto precharge co mm an d bank b read with auto precharge co mm an d bank b cax rby rbz cbz
etrontech 1m x 16 sdram em636165 preliminary 55 rev. 1.8 nov 2001 figure 16.2. auto precharge after read burst (burst length=4, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck2 activate command bank a activate command bank a bx0 bx1 bx2 bx3 ay1 ay2 hi-z read command bank a rax rax rbx ax0 ax1 ax2 ax3 ay0 ay3 by0 activate command bank b activate command bank b rbx cbx rby ray cby by1 by2 by3 high az0 az1 az2 read with auto precharge command bank b read with auto precharge command bank a read with auto precharge co mm and bank b read with auto precharge command bank a cax rby raz caz raz
etrontech 1m x 16 sdram em636165 preliminary 56 rev. 1.8 nov 2001 figure 16.3. auto precharge after read burst (burst length=4, cas# latency=3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# a10 a0~a9 dqm dq a11 t ck3 activate co mm an d bank a bx0 bx1 bx2 bx3 ay1 ay2 hi-z read co mm an d bank a rax rax rbx ax0 ax1 ax2 ax3 ay0 ay3 by0 activate co mm an d bank b activate co mm an d bank b rbx cbx by1 by2 by3 high read with auto precharge co mm an d bank b read with auto precharge co mm an d bank a read with auto precharge co mm an d bank b cax rby cby rby cay we#
etrontech 1m x 16 sdram em636165 preliminary 57 rev. 1.8 nov 2001 figure 17.1. auto precharge after write burst (burst length=4, cas# latency=1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck1 activate co mm an d bank a dbx0 dbx1 dbx2 dbx3 day1 day2 hi-z write co mm an d bank a rax rax rbx dax0 dax1 dax2 dax3 day0 day3 dby0 activate co mm an d bank b activate co mm an d bank b cbx cay dby1 dby2 dby3 high write with auto precharge co mm an d bank b write with auto precharge co mm an d bank a write with auto precharge co mm an d bank b rby caz cby rby daz0 daz0 activate co mm an d bank a write with auto precharge co mm an d bank a daz0 daz0 cax rbx raz raz t11
etrontech 1m x 16 sdram em636165 preliminary 58 rev. 1.8 nov 2001 figure 17.2. auto precharge after write burst (burst length=4, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# a10 a0~a9 dqm dq a11 t ck2 activate co mm an d bank a dbx0 dbx1 dbx2 dbx3 day1 day2 hi-z write co mm an d bank a rax rax rbx dax0 dax1 dax2 dax3 day0 day3 dby0 activate co mm an d bank b activate co mm an d bank b cbx cay dby1 dby2 dby3 high write with auto precharge co mm an d bank b write with auto precharge co mm an d bank a write with auto precharge co mm an d bank b rby cby rby daz0 daz1 activate co mm an d bank a write with auto precharge co mm an d bank a daz2 daz3 cax rbx caz raz raz we#
etrontech 1m x 16 sdram em636165 preliminary 59 rev. 1.8 nov 2001 figure 17.3. auto precharge after write burst (burst length=4, cas# latency=3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a9 a0~a9 dqm dq a11 t ck3 activate co mm an d bank a dbx0 dbx1 dbx2 dbx3 day1 day2 hi-z write co mm an d bank a rax rax rbx dax0 dax1 dax2 dax3 day0 day3 dby0 activate co mm an d bank b activate co mm an d bank b cbx dby1 dby2 dby3 high write with auto precharge co mm and bank b write with auto precharge co mm an d bank a write with auto precharge co mm an d bank b cay cax rbx cby rby rby `
etrontech 1m x 16 sdram em636165 preliminary 60 rev. 1.8 nov 2001 figure 18.1. full page read cycle (burst length=full page, cas# latency=1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 activate co mm an d bank a ax ax+1 bx bx+1 bx+3 bx+4 hi-z rea d co mm an d bank a rax rax rbx ax+1 ax+2 ax-2 ax-1 bx+2 bx+5 activate co mm an d bank b burst stop co mm an d cbx high read co mm an d bank b precharge co mm an d bank b cax rbx rby rby ax bx+6 bx+7 the burst counter wraps from the highest order page address back to zero during this time interval full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. activate co mm an d bank b t ck1 t rrd t rp
etrontech 1m x 16 sdram em636165 preliminary 61 rev. 1.8 nov 2001 figure 18.2. full page read cycle (burst length=full page, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 activate co mm and bank a ax ax+1 bx bx+1 bx+3 bx+4 hi-z rea d co mm an d bank a rax rax ax+1 ax+2 ax-2 ax-1 bx+2 bx+5 activate co mm an d bank b burst stop co mm an d cbx high rea d co mm an d bank b precharge co mm an d bank b rbx cax rby rby ax bx+6 the burst counter wraps from the highest order page address back to zero during this time interval full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. activate co mm an d bank b t ck2 t rp rbx
etrontech 1m x 16 sdram em636165 preliminary 62 rev. 1.8 nov 2001 figure 18.3. full page read cycle (burst length=full page, cas# latency=3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 activate co mm an d bank a ax ax+1 bx bx+1 bx+3 bx+4 hi-z read co mm an d bank a rax rax ax+1 ax+2 ax-2 ax-1 bx+2 bx+5 activate co mm an d bank b burst stop co mm an d cbx high rea d co mm an d bank b precharge co mm an d bank b rbx cax rby rby ax the burst counter wraps from the highest order page address back to zero during this time interval full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. activate co mm an d bank b t ck3 t rp rbx
etrontech 1m x 16 sdram em636165 preliminary 63 rev. 1.8 nov 2001 figure 19.1. full page write cycle (burst length=full page, cas# latency=1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 dax+1 dax activate co mm an d bank a hi-z activate co mm an d bank b rax rax burst stop co mm an d cbx high write co mm an d bank b precharge co mm an d bank b rbx cax rby rby the burst counter wraps from the highest order page address back to zero during this time interval full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. activate co mm an d bank b t ck1 dax+2 dax+3 dax-1 dax dax+1 dbx dbx+1dbx+2dbx+3dbx+4 dbx+5 dbx+6 dbx+ 7 write co mm an d bank a data is ignored rbx
etrontech 1m x 16 sdram em636165 preliminary 64 rev. 1.8 nov 2001 figure 19.2. full page write cycle (burst length=full page, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 dax+ 1 dax activate co mm an d bank a hi-z activate co mm an d bank b rax rax burst stop co mm an d cbx high write co mm an d bank b precharge co mm an d bank b rbx cax rby rby the burst counter wraps from the highest order page address back to zero during this time interval full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. activate co mm an d bank b t ck2 dax+ 2 dax+ 3 dax-1 dax dax+1 dbx dbx+1 dbx+ 2 dbx+3 dbx+4 dbx+5 dbx+ 6 write co mm an d bank a data is ignored rbx
etrontech 1m x 16 sdram em636165 preliminary 65 rev. 1.8 nov 2001 figure 19.3. full page write cycle (burst length=full page, cas# latency=3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 dax+ 1 dax activate co mm an d bank a hi-z activate co mm an d bank b rax rax burst stop co mm an d cbx high rbx cax write co mm an d bank b precharge co mm an d bank b rby rby the burst counter wraps from the highest order page address back to zero during this time interval full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. activate co mm an d bank b t ck3 rbx dax+2 dax+3 dax-1 dax dax+1 dbx dbx+ 1 dbx+ 2 dbx+ 3 dbx+ 4 dbx+ 5 write co mm an d bank a data is ignored
etrontech 1m x 16 sdram em636165 preliminary 66 rev. 1.8 nov 2001 figure 20. byte write operation (burst length=4, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 ldqm udqm a11 rax rax cay high cax t ck2 caz activate co mm an d bank a rea d co mm an d bank a upper 3 bytes are masked write co mm an d bank a upper 3 bytes are masked rea d co mm an d bank a lower byte is masked lower byte is masked lower byte is masked ax0 ax1 ax2 ax1 ax2 ax3 day1 day2 day0 day1 day3 az1 az2 az1 az2 az0 az3 dq0 - dq7 dq8 - dq15
etrontech 1m x 16 sdram em636165 preliminary 67 rev. 1.8 nov 2001 figure 21. random row read (interleaving banks) (burst length=2, cas# latency=1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a8 dqm dq a11 high t ck1 bu0 bu1 au0 au1 bv0 bv1 av0 av1 bw0 bw1 aw0 aw1 bx0 bx1 ax0 ax1 by0 by1 ay0 ay1 bz0 activate co mm an d bank b rea d bank b with auto precharge activate co mm an d bank a read bank a with auto precharge activate co mm an d bank b read bank b with auto precharge activate co mm an d bank a read bank a with auto precharge activate co mm an d bank b read bank b with auto precharge activate co mm an d bank a read bank a with auto precharge activate co mm an d bank b read bank b with auto precharge activate co mm an d bank a read bank a with auto precharge activate co mm an d bank b read bank b with auto precharge activate co mm an d bank a read bank a with auto precharge activate co mm an d bank b read bank b with auto precharge activate co mm an d bank a rbu rbu cbu rau rau cau rbv rbv cbv rav rav cav rbw rbw cbw raw raw caw rbx rbx cbx rax rax cax rby rby cby ray ray cay rbz rbz cbz raz raz t rp t rp t rp t rp t rp t rp t rp t rp t rp t rp begin auto precharge bank b begin auto precharge bank a begin auto precharge bank b begin auto precharge bank a begin auto precharge bank b begin auto precharge bank a begin auto precharge bank b begin auto precharge bank a begin auto precharge bank b begin auto precharge bank a
etrontech 1m x 16 sdram em636165 preliminary 68 rev. 1.8 nov 2001 figure 22. full page random column read (burst length=full page, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a8 dqm dq a11 t ck2 ax0 bx0 ay0 ay1 by0 by1 az0 az1 az2 bz0 bz1 bz2 activate co mm an d bank a rea d co mm an d bank a activate co mm and bank b rea d co mm and bank b read co mm an d bank b read co mm an d bank a read co mm and bank b precharge command bank b (precharge temination) t rp read co mm an d bank a activate co mm an d bank b t rrd t rcd rax rax rbx rbx cax cbx cay cby caz cbz rbw rbw
etrontech 1m x 16 sdram em636165 preliminary 69 rev. 1.8 nov 2001 figure 23. full page random column write (burst length=full page, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck2 dax0 dbx0 day0 day1 dby0 dby1 daz0 daz1 daz2 dbz0 dbz1 dbz2 activate co mm an d bank a write co mm an d bank a activate co mm an d bank b write co mm an d bank b write co mm an d bank b write co mm an d bank a write co mm an d bank b precharge command bank b (precharge temination) t rp write co mm an d bank a activate co mm an d bank b t rrd t rcd rax rax rbx rbx cax cbx cay cby caz cbz rbw rbw t wr write data is masked
etrontech 1m x 16 sdram em636165 preliminary 70 rev. 1.8 nov 2001 figure 24.1. precharge termination of a burst (burst length=full page, cas# latency=1) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck1 dax0 dax1 dax2 dax3 dax4 ay0 ay1 ay2 daz3 daz2 daz0 activate co mm an d bank a write co mm an d bank a precharge co mm an d bank a read co mm an d bank a precharge co mm an d bank a write co mm an d bank a rax rax ray cax ray cay raz daz1 daz4 daz5 daz6 daz7 precharge termination of a write burst. write data is masked. activate co mm an d bank a activate co mm an d bank a t wr t rp t rp precharge termination of a read burst. raz caz
etrontech 1m x 16 sdram em636165 preliminary 71 rev. 1.8 nov 2001 figure 24.2. precharge termination of a burst (burst length=8 or full page, cas# latency=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a8 dqm dq a11 t ck2 dax0 dax1 dax2 dax3 ay2 ay0 ay1 activate co mm an d bank a write co mm an d bank a precharge co mm an d bank a read co mm an d bank a precharge co mm an d bank a activate co mm an d bank a rax rax ray cax ray cay az0 az1 az2 precharge termination of a write burst. write data is masked. activate co mm an d bank a t wr t rp t rp raz caz high read co mm an d bank a precharge co mm an d bank a precharge termination of a read burst trp raz
etrontech 1m x 16 sdram em636165 preliminary 72 rev. 1.8 nov 2001 figure 24.3. precharge termination of a burst (burst length=4, 8 or full page, cas# latency=3) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clk cke cs# ras# cas# we# a10 a0~a9 dqm dq a11 t ck3 dax0 ay0 ay1 ay2 activate co mm an d bank a write co mm an d bank a precharge termination of a write burst read co mm an d bank a precharge co mm an d bank a rax rax ray cax ray cay write data is masked activate co mm an d bank a t wr t rp t rp raz raz high activate co mm an d bank a precharge co mm an d bank a precharge termination of a read burst dax1
etrontech 1m x 16 sdram em636165 preliminary 73 rev. 1.8 nov 2001 50 pin tsop ii package outline drawing information y 50 1 d e h e 0.254 ? l l 1 a a 1 a 2 sb e l l 1 c 25 26 symbol dimension in inch dimension in mm min normal max min normal max a 0.048 1.20 a1 0.002 0.005 0.008 0.05 0.125 0.20 a2 0.037 0.042 0.94 1.07 b 0.012 0.015 0.018 0.3 0.375 0.45 c 0.006 0.155 d 0.82 0.825 0.83 20.82 20.95 21.08 e 0.395 0.400 0.405 10.03 10.16 10.29 e 0.031 0.80 he 0.455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.020 0.024 0.40 0.50 0.60 l1 0.0315 0.80 s 0.035 0.88 y 0.004 0.10 0 5 0 5 notes : 1. dimension d&e do not include interiead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. dimension s includes end flash. 4. controlling dimension : mm
etrontech 1m x 16 sdram em636165 preliminary 74 rev. 1.8 nov 2001 ] 765432 123456 top view a1 corner bottom view = 0.30 0.16 0.08 m m c cab a1 corner 0.65 3.90 a b 0.10(4x) seating plane 0.10 1 7 j k l m n p r j k l m n p r c c 1mx16 sdram package diagrams 60-ball (6.4mm x 10.1mm)vfbga units in mm c

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